This invention relates to the synchronization process in a Wideband CDMA system, and more particularly, to achieving slot synchronization in a Wideband CDMA system in the presence of large initial frequency errors using a matched filter having a reduced coherence window and a circular sliding integrator.
In a cellular communications system using Wideband code division multiple access (W-CDMA) protocols, a first search code (FSC) of 256 chips long is transmitted in every time slot. By synchronizing to the FSC of the received signal, a mobile station can identify the time slot boundary of the downlink signals. Typically, a FSC matched filter is used to synchronize to the FSC. FSC synchronization is done by identifying the peaks of the FSC matched filter output. However, because the accuracy of an oscillator used in a mobile station is typically in the range of 2.5 to 15 parts per million (ppm), the FSC synchronization must often be performed in the presence of large frequency errors.
The working assumption for the oscillator accuracy is 10 ppm. Since the operating frequency for current W-CDMA systems, for example, the IMT-2000 system, is 1.9-2.0 GHz, using a 10 ppm oscillator results in initial frequency errors of up to 20 KHz. As 1 FSC symbol is of duration 0.0625 milliseconds, a 20 KHz frequency error causes up to a 450xc2x0 phase rotation per periodic channel symbol, thereby severely degrading performance of the FSC matched filter. Current matched filters are able to tolerate frequency errors of up to 5 KHz before the phase rotation per chip due to the frequency error degrades performance of the matched filter. Thus, a mobile station needs to hypothesize oscillator frequency errors and adjust its oscillator frequency according to each hypothesis such that the actual frequency error for the best hypothesis is less than 5 KHz. This requires the mobile station to make up to 4 frequency error hypotheses before finding the slot boundary, where each frequency hypothesis is verified by checking the CRC code, thereby greatly increasing power consumption and synchronization time.
Because the same FSC is used by all of the cells and sectors, and occurs in the same position of every time slot, the FSC is used to find the location of slot boundaries. An accumulator accumulates the output of the FSC matched filter over a specified number of time slots, thereby overcoming noise in the received signal as the energy peaks due to the FSC accumulate faster than the energy peaks due to noise. However, due to the inaccuracy of the oscillator and multipath interference, the position where the peaks occur changes gradually, resulting in the energy peaks accumulated by the accumulator being dispersed over multiple time indices.
Additionally, noise in the received signal could result in energy peaks in the FSC matched filter output greater than those due to the FSC, even after accumulation. This increases the probability that the wrong time index will be sent to the next stage of synchronization, thereby resulting in misidentification of the time slot boundary.
The invention is directed to overcoming one or more of the problems discussed above in a novel and simple manner.
In accordance with the invention, a receiver uses a first search code (FSC) matched filter having a reduced coherence window to reduce a phase rotation of a received signal resulting from an oscillator error. Additionally, the receiver uses a circular sliding integrator to combine energy dispersed during the accumulation process as a result of the oscillator error and multipath interference. Further, a sorter determines a predefined number of largest energy peaks from an output of the circular sliding integrator, eliminating those energy peaks resulting from the circular sliding integrator, thereby increasing the probability of a time index representing a time slot boundary being sent to a next stage of the synchronization process.
Broadly, there is disclosed herein a receiver for improving slot synchronization in a Wideband code division multiple access (W-CDMA) communications system by overcoming oscillator error and multipath interference, the receiver having a matched filter for receiving a signal including a FSC, where the matched filter utilizes a reduced coherence window for decreasing the degradation of a symbol due to a carrier phase rotation resulting from the oscillator error. The receiver further includes an accumulator coupled to the matched filter for accumulating an output of the matched filter over an accumulation window of time slots. A circular sliding integrator is coupled to the accumulator for combining dispersed energy from an output of the accumulator over an integration window. Additionally, a sorter is coupled to the circular sliding integrator for determining a specified number of candidate time indices for a time slot boundary using an output of the circular sliding integrator.
It is a feature of the invention that the matched filter is a FSC matched filter.
It is another feature of the invention that the size of the coherence window is determined using a desired phase rotation within the coherence window, a chip duration and an actual frequency error due to the oscillator.
It is another feature of the invention that the matched filter includes a shift register having a number of elements less than a number of chips forming the symbol, for holding a portion of the received signal. The matched filter further includes a multiplying-integrating processing circuit coupled to the shift register for multiplying the portion of the received signal in the shift register with a portion of the FSC, and integrating the products. Further, the matched filter includes a phase elimination circuit coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit.
It is yet another feature of the invention that the circular sliding integrator is a first integrator, and the receiver includes a shift register having a number of elements equal to a number of chips comprising the symbol for receiving the received signal. The receiver further includes a buffer coupled to the shift register for receiving a portion of the received signal from the shift register, a multiplying-integrating processing circuit coupled to the buffer for multiplying the portion of the received signal in the buffer with a portion of the FSC, and integrating the products. The receiver further includes a phase elimination circuit coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit, a storage device coupled to the phase elimination circuit for storing a result produced by the phase elimination circuit, and a second integrator coupled to the storage device for integrating the stored results.
It is a further feature of the invention that the size of the accumulation window is determined using a signal-to-noise ratio.
It is still another feature of the invention that the size of the integration window is determined using the oscillator error, a chip duration and size of the accumulation window.
There is disclosed in accordance with another aspect of the invention a receiver for improving initial slot synchronization in a W-CDMA communications system by overcoming oscillator error. The receiver includes a matched filter for receiving a signal including a FSC, the matched filter utilizing a reduced coherence window for decreasing the degradation of a symbol due to a carrier phase rotation resulting from the oscillator error. An accumulator is coupled to the matched filter for accumulating an output of the matched filter over an accumulation of time slots, and an integrator is coupled to the accumulator for combining dispersed energy from an output of the accumulator over an integration window.
It is a feature of the invention that the matched filter is a FSC matched filter.
It is a feature of the invention that the size of the coherence window is determined using a desired phase rotation within the coherence window, a chip duration and an actual frequency error due to the oscillator.
It is another feature of the invention that the matched filter includes a shift register having a number of elements less than a number of chips forming the symbol for holding a portion of the received symbol. A multiplying-integrating processing circuit is coupled to the shift register for multiplying a portion of the received signal in the shift register with a portion of the FSC, and integrating the products. And a phase eliminator circuit is coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit.
It is yet another feature of the invention that the circular sliding integrator is a first integrator, and the receiver includes a shift register having a number of elements equal to a number of chips comprising the symbol for receiving the received signal. The receiver further includes a buffer coupled to the shift register for receiving a portion of the received signal from the shift register, a multiplying-integrating processing circuit coupled to the buffer for multiplying the portion of the received signal in the buffer with a portion of the FSC, and integrating the products. The receiver further includes a phase elimination circuit coupled to the multiplying-integrating processing circuit for removing phase information from a result produced by the multiplying-integrating processing circuit, a storage device coupled to the phase elimination circuit for storing a result produced by the phase elimination circuit, and a second integrator coupled to the storage device for integrating the stored results.
It is a further feature of the invention that the receiver includes a sorter coupled to the integrator for determining a specified number of candidate time indices for a time slot boundary using an output of the integrator.
In another embodiment of the invention, a receiver for improving initial slot synchronization in a W-CDMA communications system by overcoming oscillator error includes a matched filter receiving a signal including a FSC, where the matched filter decreases the degradation of a symbol due to a carrier phase rotation resulting from the oscillator error. An accumulator is coupled to the matched filter, the accumulator including a predetermined number of storage locations for accumulating an output of the matched filter over an accumulation window of time slots. An integrator is coupled to the accumulator for combining dispersed energy from an output of the accumulator over an integration window.
It is a feature of the invention that the size of the integration window is determined using an oscillator error and size of the accumulation window.
It is another feature of the invention that the predetermined number of storage locations equal the number of chips per slot, and the integrator is a sliding integrator wherein the integration window moves across the predetermined number of storage locations. The sliding integrator may be a circular sliding integrator, wherein when the integration window extends beyond a final storage location, the integration window extends to a first storage location, thereby operating in a circular fashion.
It is a further feature of the invention that a sorter is coupled to the integrator for determining a specified number of candidate time indices for a time slot boundary using an output of the integrator.
Broadly, there is disclosed herein a method for improving slot synchronization in a W-CDMA communications system by overcoming oscillator error and multipath interference. The method includes receiving a signal including a FSC. The received signal is filtered using a matched filter having a reduced coherence window. The filtered signal is accumulated over an accumulator window of time slots to overcome noise in the filtered signal, and the accumulated signal is integrated over an integration window to combine dispersed energy in the accumulated signal.
It is a feature of the invention that filtering the received signal includes filtering the received signal using a FSC matched filter.
It is another feature of the invention that filtering the received signal includes shifting a portion of the received signal into a shift register, multiplying a portion of the received signal with a portion of the FSC, integrating the products using a multiplying-integrating processing circuit, and removing phase information from a result produced by the multiplying-integrating processing circuit using a phase elimination circuit.
It is a further feature of the invention that the step of filtering the received signal includes shifting the received signal into a shift register, buffering a portion of the received signal from the shift register, and multiplying the portion of the received signal with a portion of the FSC and integrating the products using a multiplying-integrating processing circuit. The step of filtering further includes removing phase information from a result produced by the multiplying-integrating processing circuit using a phase elimination circuit, storing the result of the phase elimination circuit, and integrating the stored results.
It is yet an additional feature of the invention that accumulating the filtered signal includes determining a signal-to-noise ratio for the received signal.
In yet a further aspect of the invention, integrating the accumulated signal further includes moving the integration window across memory locations storing the accumulated signal. Additionally, moving the integration window may include extending the integration window to a first storage location for the accumulated signal when the integration window extends beyond a final storage location for the accumulated signal.
In yet a further aspect of the invention, a specified number of candidate time indices is determined for a time slot boundary using the integrated signal.
In still a further aspect of the invention, determining the specified number of candidate time indices further includes determining a first candidate time index for a largest integrator output value, zeroing out neighboring index values of the first candidate time index, determining an additional candidate time index for a next largest integrator output value, and zeroing out the neighboring time index values of the additional candidate time index. Determining additional candidate time indices for the next largest integrator output values and zeroing out the neighboring time indices is repeated until the specified number of candidate time indices is reached.
In another feature of the invention, the specified number of determined candidate time indices is communicated to a second stage synchronizer.